1. Field of the Invention
The present invention relates to a semiconductor module. Specifically, the invention relates to a semiconductor module including a plurality of semiconductor chips.
2. Description of the Related Art
A DC-DC converter for use in synchronous rectification or the like is known.
FIG. 14 schematically shows a commonly-used circuit of the above DC-DC converter. As shown in FIG. 14, a capacitor Cin is connected between an input terminal Vin to which an input voltage is applied and a ground. The input terminal Vin is connected to the drain of an N-type MIS (metal insulator semiconductor) transistor Q1 whose channel (current path) is of an N type. The MIS transistor includes a MOS (metal oxide semiconductor) transistor. The gate of the MIS transistor Q1 is connected to an IC for DC-DC conversion. The MIS transistor Q1 functions as a switching device.
The source of the MIS transistor Q1 is connected to the drain of an N-type MIS transistor Q2. The source of the MIS transistor Q2 is connected to the ground and the gate thereof is connected to the IC.
A connection node N1 between the source of the MIS transistor Q1 and the drain of the MIS transistor Q2 is connected to the cathode of a diode D1. The anode of the diode D1 is connected to the ground. The connection node N1 is connected to an output terminal Vout via an inductance L. A capacitor Cout is connected in parallel between the output terminal Vout and the ground. RL indicates a load resistance.
In the foregoing circuit, the MIS transistor Q1 is implemented by a single semiconductor chip 41 and the MIS transistor Q2 is done by a single semiconductor chip 42. Each of the MIS transistors has a known vertical structure as shown in FIG. 15. In this structure, a drain electrode is formed on the bottom of each of the semiconductor chips 41 and 42. In FIG. 15, reference symbols S, D and G denote a source, a drain and a gate, respectively.
FIG. 16A schematically shows an outward appearance of a semiconductor module having semiconductor chips 41 and 42 according to first prior art, and FIG. 16B schematically shows an internal structure of the semiconductor module. The first prior is shown taking a known SOP-8 package as an example. In FIG. 16A, reference numeral 43 indicates a package (envelope) and reference numeral 44 denotes an external connecting terminal part of which is exposed to the semiconductor module. Referring to FIG. 16B, the semiconductor chip 41 or 42, which has the transistor structure as shown in FIG. 15, is mounted on a conductive frame 45 such that the bottom of the chip 41 or 42 contacts the frame 45. The frame 45 is connected to the external connecting terminal 44, and the semiconductor chip 41 or 42 is connected to the external connecting terminal 44 through a wire 46.
As described above, the bottom of the semiconductor chip 41 or 42 serves as a drain electrode. On the other hand, the source of the MIS transistor Q1 and the drain of the MIS transistor Q2 are connected to each other in the DC-DC converter shown in FIG. 14. For this reason, it is impossible to mount the semiconductor chips 41 and 42 on the frame 45 with the frame serving as a common potential. Under present circumstances, the semiconductor chips 41 and 42 are separately sealed with their respective semiconductor modules, and these modules are connected to each other by a wire or the like on a mounting substrate.
It has recently been desired that electronic components such as semiconductor modules be decreased in number and size and increased in operation speed in accordance with miniaturization and high-speed operation of electronic equipment using the above semiconductor modules. To seal the semiconductor chips with separate packages as in the first prior art described above is however contrary to a reduction in component count. The number of wires should be decreased to operate the electronic equipment at high speed. In the first prior art, however, the two semiconductor modules have to be connected to each other by a wire, which prevents the high-speed operation.
FIG. 17 schematically shows the interior of a semiconductor module according to second prior art in order to describe a method of packaging semiconductor chips. Referring to FIG. 17, in the second prior art, two frames 45 are provided and semiconductor chips 41 and 42 are mounted on the frames 45, respectively. The frames 45 are connected to the semiconductor chips 41 and 42 appropriately by wires so as to achieve the circuit arrangement shown in FIG. 14. By doing so, a single semiconductor module can be obtained; however, given wiring is required inside or outside the semiconductor module and the semiconductor module cannot operate at high speed. Since, moreover, an interval Z between the frames 45 depends upon the power supply voltage or the potential of each of the frames, it cannot be set to not larger than a given value, thus imposing restrictions on miniaturization of the semiconductor module.